The production of current electronic integrated circuits, which can include a very large number of electronic components, is generally done using computer-aided design software (CAD Tool) making it possible to modelise the different elements of those circuits and making it possible, in a final step, to generate a set of computer files which will be used to produce masks, such as lithography masks. These masks will further on be used during the manufacturing of such integrated circuits.
Such software use one or several libraries of standard cells corresponding to electronic devices. A library of cells dedicated to the realisation of digital logic circuits generally includes cells performing a more or less complex logic function (AND, OR, NOT, . . . logic gate) or an information storage function (latches).
Usually, in a library, several descriptions and models of each cell are available in the form of different files used by the various software tools during the software design method of an integrated circuit.
Each cell in particular includes a physical description (layout) of the electronic device represented by the cell, i.e. the arrangement of the various elements forming the active and/or passive components of the electronic device, for example several transistors, the internal electrical connections between those components and connection elements connected to the inputs and outputs of the electronic device.
Each cell has also associated descriptions of its electrical behavior, generally by way of different files precising timing, power or other features.
During the integrated circuit manufacturing, electronic devices are made in a stack of layers comprising a semiconductor layer. For example, when the electronic device is a logic gate comprising several transistors, the active zones (source, drain, channel) of the transistors are formed by doped regions of said semiconductor layer. The semiconductor layer is covered with at least one dielectric layer in which electrically conductive portions are arranged. The connections can be internal electrical connections connecting the various components of the electronic device to one another. These connections can also connect, via connection elements passing through the dielectric layer, the inputs and outputs of the electronic device to electrically conductive input and output contacts, for example metal ones, arranged above the dielectric layer. Some other conductive portions are made in upper dielectric layers to realize interconnections between electrical devices of the integrated circuit.
One of the steps of the CAD conception of electronic integrated circuits uses a place-and-route software. This place-and-route software in particular uses computer files providing the physical description, or representation, of all or part of each cell represented in two dimensions (2D) (e.g. “layout” files). The role of this place-and-route software is to position the 2D physical representations of the cells of the integrated circuit to be manufactured alongside each other, in a same plane.
In practice, the components of each cell fit, after physical manufacturing of the circuit, into a portion of the stack of layers making up the circuit generally a rectangle parallelepiped portion. The 2D physical description of each cell substantially corresponds to a “projection” of the elements making up the components of the cell on a same rectangular surface parallel to the top surface of the integrated circuit. The surfaces of the “projected” elements correspond for example to the surface occupied by the active zones of the semiconductor layer, the surface occupied by the electrically conductive portions arranged in the dielectric layer, the surface of the polysilicon portions deposited on the semiconductor layer and forming the gates of the transistors, etc. All the surfaces corresponding to an element projection are inside a rectangle surface delimited by a boundary rectangle.
One of the dimensions of this boundary, generally the height, is identical for all of the cells of a same library. Indeed, the cells are placed next to each other to form rows of cells, all the rows having the same height. The other dimension of this boundary, for example the width, varies for each cell as a function of the complexity of the associated electronic device, this complexity for example being related to the number of transistors and internal electrical connections of the electronic device.
One example of layout of such a cell 10 is shown in FIG. 1. This cell 10 occupies an area with width L, and height H similar to the height of the other cells of the library to which the cell 10 belongs. In a given library, the height H is generally defined from the most complex cell (for example a latch). This area is defined on top and on bottom by electrically conductive electrical power lines 12, one for example being intended to be connected to a power voltage and the other one connected to the mass.
The cell 10 includes a first P doped active zone 16, with height HNdiff, in which NMOS transistors are made and a second N doped active zone 18, with height HPdiff, in which PMOS transistors are made (the doping type of the active zones corresponding to the doping type of the transistor channel). The cell 10 also includes polysilicon portions 20 deposited on the active zones 16 and 18 and forming gates common to the PMOS and NMOS transistors made in the active zones 16 and 18. Lastly, the cell 10 also includes electrical connection elements 22 extending perpendicular to the plane of the surface with width L and height H of the cell, intended to be electrically connected to input/output contacts of the electronic device. These connection elements 22 here produce an electrical connection between the gates of the transistors of the cell 10 and the input/output contacts, and are formed between the active zones 16 and 18, in a reserved zone with height HIO.
The different elements of the cell 10 (electrical power lines 12, active zones 16 and 18, connection elements 22) are spaced apart from each other to avoid any short circuit between them.
In the place-and-route software, the layouts of the cells are arranged next to each other forming several rows of cells parallel to each other. FIG. 2 illustrates several cells arranged in two parallel rows. In this FIG. 2, four first cells 10.1 to 10.4 are arranged next to each other forming a first row and four second cells 10.5 to 10.8 are arranged next to each other forming a second row. Electrical power lines 12.1 to 12.3 are made continuously for each row of cells and are therefore shared by all of the cells of a same row. Moreover, the electrical power lines can be shared by two adjacent rows of cells. Thus, in the example of FIG. 2, the electrical power line 12.2 shared by the first and second rows is for example electrically connected to the mass. The electrical power lines 12.1 and 12.3 are electrically connected to the supply voltage and may be shared with other adjacent rows of cells not shown in FIG. 2.
Each cell 10.1 to 10.4 also includes connection elements 22 arranged between the power lines 12.1 and 12.2. Likewise, each cell 10.5 to 10.8 includes connection elements 22 arranged between the power lines 12.2 and 12.3 of said cells.
In order to densify the integrated circuits, it is known to produce three-dimensional integrated circuits on several levels, each level being able to correspond to a stack of layers comprising a semiconductor layer covered with a dielectric layer in which electrically conductive portions are arranged intended to form electrical interconnections.
A first manner to manufacture such integrated circuits, called parallel 3D integration, consists in assembling 2 or more integrated circuits made separately, each circuit being made using a standard CAD flow. The different circuits are electrically connected to one another through electrically conductive vias formed beforehand, for example using TSV (“Through Silicon Via”) technology through the different levels.
Parallel 3D integration has several drawbacks. First of all, this type of integration is costly to carry out. Moreover, the electrically conductive vias necessary to realize the electrical connections between the different levels of the integrated circuit are very bulky, this bulk generally being between about 5 μm and 10 μm. Lastly, the alignments done between the levels are not very precise, which limits this integration to the superposition of complex circuits or functional blocks that do not require very precise alignment.
A second way of manufacturing three dimensional integrated circuits, called 3D monolithic integration uses “3D” standard cells corresponding to electronic devices in which the components, for example the transistors, of each electronic device are distributed over two or more levels, and more particularly inside or on two distinct semiconducting layers.
An example of the layout of such a 3D standard cell 30 is shown in FIG. 3. The cell 30 here comprises the same structural elements as the cell 10 previously described. The 3D cell 30 occupies a surface with width L and height H. As for the cell 10 previously described, the area occupied by the cell 30 is delimited on top and on bottom by the electrical power lines 12.
The cell 30 includes a first N doped active zone 32, with height HPdiff, in which PMOS transistors are produced, and a second P doped active zone 34, with height HNdiff, in which NMOS transistors are produced. The first N doped active zone 32 is made in a first semiconductor layer that is part of a first stack of layers, the second P doped active zone 34 being produced in a second semiconductor layer that is part of a second stack of layers arranged above the first stack of layers.
The cell 30 also includes polysilicon portions 36 deposited on the second semiconductor layer and forming NMOS transistor gates (the cell 30 also includes polysilicon portions, not shown in FIG. 3, deposited on the first semiconductor layer and forming PMOS transistor gates). Lastly, the cell 30 also includes connection elements 38 extending perpendicular to the plane of the surface of the cell 30 with width L and height H intended to be electrically connected to input/output contacts of the electronic device represented by the cell 30 that are placed above the second stack of layers. These connection elements 38 are electrically connected to the polysilicon portions 36, and are placed between the active zones 32, 34 and the metal supply line 12 located at the bottom of the cell 30, in a reserved zone with height HIO.
Such a 3D standard cell 30 can be seen as corresponding to the standard cell 10 that would be “folded” in 2, by arranging all of the NMOS transistors above the PMOS transistors of the cell 30. The height Hact3D necessary to realize active zones of said cell 30 is smaller than the height Hact2D of the cell 10 previously described.
In the following description, we will call “2D” cell, an electronic device having components manufactured on or inside a unique semiconductor layer, and “3D” cell, an electronic device having components manufactured on or inside 2 or more semiconductor layers.
The design of an integrated circuit from 3D standard cells, using CAD tools, is similar to that produced from traditional 2D cells. In the place-and-route software, these 3D cells are therefore arranged in rows next to each other in a plane representing the two stacks of superimposed layers, similarly to FIG. 2.